Semicoductor radiating substrate and production method therefor and package

ABSTRACT

In a semiconductor heat-dissipating substrate made of a Cu—W alloy whose pores have been infiltrated with copper, being a porous tungsten body whose pore diameter at a specific cumulative surface area of 95% is 0.3 μm or more, and whose pore diameter at a specific cumulative surface area of 5% is 30 μm or less, thermal conductivity of 210 W/m·K or more is obtained by decreasing the content of iron-family metal to be less than 0.02 weight %. Likewise, changing the amount of infiltrated copper in a molded object by utilizing a multi-shaft press to vary the amount of vesicles in the middle and peripheral portions makes for offering at low cost a semiconductor heat-dissipating substrate that in between middle and peripheral portions made of different materials does not have bonding matter.

TECHNICAL FIELD

[0001] The present invention relates to: semiconductor heat-dissipatingsubstrates that are superiorly heat dissipative and suitable forhigh-frequency devices and for semiconductor light-emitting devices,whose semiconductor elements produce a large amount of heat; tomanufacturing methods therefor; and to packages and submounts, as wellas semiconductor devices, utilizing the substrates.

BACKGROUND ART

[0002] While semiconductors have taken on widely spanning roles asarithmetic elements and storage devices in personal computers and othercomputers, due to the rapid spread of mobile communications and toadvances in high-capacity communications in recent years, applicationsin output devices for high-frequency amplification in base stations forthese communications forms are broadening quickly.

[0003] Semiconductor devices are generally assembled into a package madeup of a semiconductor heat-dissipating substrate, as well asinput/output terminals and seal rings, and because the Si(silicon)—bipolar semiconductors widely used to date require isolation,they have been populated onto insulating substrates made of asemiconductor substrate onto which BeO (beryllia) is bonded. On theother hand, being that they do not require isolation Si-LDMOS andGaAs-FET semiconductors, outstanding in high-frequency characteristics,may be surface-mounted directly onto semiconductor heat-dissipatingsubstrates.

[0004] Nevertheless, attendant on the heightened output fromhigh-frequency devices and semiconductor light-emitting devices inrecent years, the amount of heat issuing from these semiconductorcomponents has increased significantly, and consequently packages andheat sinks having heightened heat-dissipating properties are beingcalled for. Given such circumstances, the role of semiconductorheat-dissipating substrates is becoming more and more important; andsemiconductor heat-dissipating substrates having further heightenedthermal conductivity in order to improve their heat-dissipatingproperties are being sought.

[0005] Moreover, if a package becomes warped, because gaps will arisebetween it and the semiconductor heat-dissipating substrate onto whichfins or like devices for dissipating heat externally are attached—theheat-dissipating properties will be considerably spoiled. For example, asemiconductor heat-dissipating substrate, after being processed into thenecessary form, is normally plated with Ni, whereupon terminals forexternal connections and seal rings for airtight sealing are bonded inplace by brazing and the assembly is made into a package; a heatingprocess is generally included in the Ni-plating procedure, however, inorder to improve the adherence of the Ni plating, and due to the impactof the heat warpage is liable to occur in the package.

[0006] In brazing, furthermore, it is extremely important that thethermal expansion coefficients of the alumina, beryllia, and Fe—Ni—Coalloys used as the terminals and seal rings that are brazed, and of thesemiconductor heat-dissipating substrate are compatible. For example,although copper has a high thermal conductivity of approximately 393W/m·K, what with its thermal expansion coefficient being a large17×10⁻⁶/° C., it cannot be employed as a semiconductor heat-dissipatingsubstrate. On the other hand, alloys and composites made of copper andtungsten (referred to simply as “copper-tungsten alloys” or “Cu—Walloys” hereinafter), can be made compatible in thermal expansioncoefficient with the above-noted materials by changing the copper andtungsten percentage composition; moreover, because of their highrigidity, incidents of warping due to heat are held down, and thereforethey are widely employed as semiconductor heat-dissipating substrates.

[0007] A method of fabricating semiconductor heat-dissipating substratesfrom such Cu—W alloys is proposed in Japanese Pub. Pat. App. No.S59-141248. In particular, they are fabricated by pressure-molding apowder in which 0.02-2 weight % of an iron-family metal is added totungsten powder 1 to 40 μm in average particle diameter, andsubsequently sintering it in a non-oxidizing atmosphere into a poroussintered body, which is impregnated with copper in a weight ratio of 5to 25 weight %.

[0008] Likewise, a composite member made of a copper-tungsten alloy isproposed in Japanese Pub. Pat. App. No. H10-280082, the composite/alloymember—in particular, a non-machined or partially machined Cu—Walloy—characterized in that surfaces of the copper and tungsten havingno fractured areas are exposed over the entire peripheral surface exceptfor the crossover portions of the plurality of faces, and in that it isnot lacking in tungsten grains. The characteristics obtained with Cu—Walloys as determined by this manufacturing process are that with forexample an alloy whose thermal expansion coefficient is 6.5×10⁻⁶/° C.,the thermal conductivity is 210 W/m·K, and that the pre- andpost-Ni-plating warpage together is 0.01 mm.

[0009] In Japanese Pub. Pat. App. No. H4-348062, furthermore, aheat-dissipating semiconductor-carrier substrate, in which a pluralityof Cu—W alloy pieces are overlaid and bonded via copper, is proposed.For example, overlaying a flat plate 1, whose form is 7 mm×7 mm×0.5 mmand whose weight composition is Cu: W=20:80, and a flat plate 2, whoseform is 30 mm×11 mm×1 mm and whose weight composition is Cu: W=10:90,with copper foil sandwiched in between, and bonding by heat-fusing thecopper foil, yields a substrate stepped in form. After brazing at thesame time with an alumina frame and a beryllia plate, actual bottomwarpage in the package is supposed to be 0.002 mm or less. Likewise,proposed in Japanese Pub. Pat. App. No. H5-3265 is a compositeheat-dissipating semiconductor-carrier substrate, in which poroussintered tungsten parts of two kinds differing in density are overlaidand bonded while simultaneously being infiltrated with molten copper.

[0010] In addition, a composite heat-dissipating semiconductor-carriersubstrate characterized in that porous sintered tungsten parts of atleast two kinds differing in density are bonded by copper-infiltrationis put forth in Japanese Pub. Pat. App. No. H5-3265 as well as U.S. Pat.No. 5,481,136. What is proposed is to establish the one to contain 5 to25 weight % Cu, and the other to contain 40 to 70 weight % Cu. Inparticular, making the peripheral portion a Cu—W alloy with the greateramount of Cu is supposed to match its thermal expansion coefficient tothat of plastic packages or flexible printed-circuit boards and make forimproving the reliability of the semiconductors or packages.

[0011] Furthermore, in a semiconductor module having a metal substratethat carries a semiconductor laser-diode chip and a lens, and onto theunder part of which a Peltier element is adhered via metal solder,Japanese Pub. Pat. App. No. H10-200208 as well as U.S. Pat. No.6,219,364 proposes that utilizing a metal substrate made from a firstmetal substance whose thermal expansion coefficient is large, on anencompassing side of side of a metal component whose thermal expansioncoefficient is smaller than that of the first metal substance, serves toimprove the cooling potential and gains reliance in thermalenvironments. Brazing or penetrant-bonding the materials are waysproposed for fabricating the metal substrates.

[0012] A functionally-graded metal substrate, moreover, is proposed inU.S. Pat. No. 6,114,048. The functionally-graded metal substrate has astructure in which a minimum of two kinds of metal—wherein the thermalconductivity of the middle portion is higher than that of the peripheralportion, while the peripheral portion has a lower thermal expansioncoefficient than that of the middle portion—are composited in thehorizontal plane (x-y plane) used for mounting semiconductors.

DISCLOSURE OF INVENTION

[0013] Semiconductor heat-dissipating substrates of Cu—W alloys aregenerally manufactured, as mentioned in the above-noted Japanese Pub.Pat. App. No. S59-141248, by fabricating a porous tungsten body and thencontacting it with molten copper to infiltrate the pores within theporous tungsten body with the copper. A drawback nevertheless has beenthat iron-family metal added in order to promote infiltration of thecopper acts as a dispersant to the flow of heat, which diminishes themost important characteristic of a semiconductor heat-dissipatingsubstrate—its thermal conductivity.

[0014] In situations in which copper infiltration is carried outemploying large-scale furnaces for mass production in particular, due toso-called irregularities in manufacturing parameters, such asfluctuations in furnace interior temperature and oxygen gas flow, andthe influence of differences in charge volume, products that have notbeen completely infiltrated are sometimes produced. Iron-family metalssuch as iron, nickel and cobalt are made into solid solutions withtungsten; what is more, in order to improve the wettability of thetungsten for copper—in order to achieve adequate copperinfiltration—mixing iron-family metal with tungsten powder has beenindispensable.

[0015] Nevertheless, consequent upon the heightening of device output inrecent years, instances of conventional Cu—W alloys being inadequate inthermal conductivity as heat-dissipating substrates have arisen. Forexample, with a W-11 wt. % Cu alloy whose thermal expansion coefficientis compatible with alumina, approximately 0.2 wt. % Ni is used as anadditive metal, and the thermal conductivity is 180 W/m·K; but cases inwhich conditions cannot be met with this thermal conductivity have beenon the rise.

[0016] Here, other than being intentionally added, an iron-family metalsuch as nickel is in some cases admixed in a powder-mixing, pulverizingor like process. For example, even though with Cu—W alloy No. 3 in Table2 in the above-noted Japanese Pub. Pat. App. No. H10-280082 there is noadditive metal, 0.09 weight % iron is admixed during pulverization usingsteel balls, and this metal takes on the work of improving thewettability of tungsten for copper. At the same time, however, thethermal conductivity of the Cu—W alloy is impaired, and consequently thethermal conductivity of the Cu—W alloy stays at 210 W/m·K.

[0017] The thermal conductivity of elemental tungsten originally is 167W/m·K, and of elemental copper, 393 W/m·K, and with the aforementionedW-11 wt. % Cu alloy the theoretical limit should therefore be 220 W/m·K.The difference with the theoretical value is assumed to be on account ofthe presence of various heat-flow dissipating factors such asinterfacial and crystalline distortions, and impurities. Cu—W alloys inwhich heat dispersing factors are reduced to the utmost, and the thermalconductivity is furthermore improved have therefore been eagerly sought.

[0018] Circumstances of late have gotten to be such thatheat-dissipating substrates whose thermal conductivity is even 250 W/m·Kor more and near that of copper are being called for, but realizing thiswith conventional Cu—W elemental alloys is difficult. For this reason ithas become necessary to utilize Cu—W alloy for the parts wherecompatibility in thermal expansion coefficient with the brazing portionsis important, and to utilize highly heat-conducting copper, or else Cu—Walloy in which the amount of copper is ample, in the parts, such as theareas on which semiconductors are mounted, where heat-dissipatingcapacity is important; and many techniques regarding methods ofcompositing either copper or a number of Cu—W alloy pieces have beenproposed.

[0019] Being that compositing methods to date, however, select atechnique for obtaining a single composite material by combining anumber of either Cu—W alloy pieces or porous tungsten parts preparedbeforehand—as is noted in the previously mentioned Japanese Pub. Pat.App. No. H4-348062 and Japanese Pub. Pat. App. No. H5-3265—elevatedcosts cannot be avoided because the plurality of Cu—W alloy pieces orelse the porous tungsten parts are manufactured in separate processes.

[0020] Moreover, in compositing by combining a number of either Cu—Walloy pieces or porous tungsten parts prepared beforehand, if a brazingor like technique is adopted, a problem arises in that due to theintervention of the brazing substance or like bonding material thethermal conductivity deteriorates. There have been problems besides, inthat with the technique of joining the copper by a rolling method,controlling the thickness of each layer is problematic, and the thermalexpansion coefficient, thermal conductivity and like characteristicsfluctuate. A heat-dissipating substrate made from a low-cost,high-quality composite Cu—W alloy, and a method of manufacturing it havetherefore been eagerly sought.

[0021] In order to improve the heat-dissipating properties of asemiconductor substrate having a composite makeup, it is desirable tomake where it is directly beneath where the semiconductors are carried amaterial having a higher thermal conductivity.

[0022] With the stepped makeup mentioned in the above-noted JapanesePub. Pat. App. No. H4-348062, a structure in which directly beneath thesemiconductor-carrying portion, rather than a W-10 weight % Cu elementalmaterial, is highly heat conducting W-20 weight % Cu, wherein the amountof Cu is larger, is superiorly heat-dissipative. This structure isimpaired, however, in that heat is conducted via a W-10 weight % Cu flatplate. That is, a makeup in which heat is conveyed directly toheat-dissipating understructures such as fins—as is proposed in U.S.Pat. No. 6,114,048—excels in heat-dissipating properties.

[0023] In making this structure practicable, moreover, controllingwarpage has proved to be a mandatory issue. In particular, owing to thefact that several materials are combined in the structure, stress isliable to remain in the interior of the semiconductor substrate; andwhen the substrate heats up, because the stress is liberated, warpage isexceedingly likely to occur. Also, when by means of brazing thesubstrate is bonded with surrounding mechanical devices of alumina andelectrode material made of cobalt, warpage has been liable to occur dueto thermal expansion discrepancies, and irregularities have especiallytended to grow greater. Consequently, with technology to date,semiconductor devices have only been put to use sorted according toextent of warpage after having being assembled. Moreover, not only thesize of the warpage, but also the direction has turned out to be aproblem. In particular, warpage such that straight under thesemiconductor it is earthed is superiorly heat dissipative; but if inthe opposite direction warpage will end up inferiorly heat-dissipative,because it will be earthed from straight under the semiconductor throughgrease or the like.

[0024] Taking into consideration such circumstances to date, an objectof the present invention is to provide a heat-dissipating substrate, anda method of its manufacture, made of a Cu—W alloy in which theiron-family metal that proves to be a heat-dispersing factor is reducedand the thermal conductivity is improved over the conventional. It isalso an object to offer a low-cost, high-quality semiconductorheat-dissipating substrate, and a method of its manufacture, in which aplurality of Cu—W alloys, or it and copper is combined to furtherheighten the thermal conductivity.

[0025] In order to achieve the above-noted objective, a firstsemiconductor heat-dissipating substrate that the present inventionprovides is made of a copper-tungsten alloy being a porous tungsten bodyinto the pores of which copper has been infiltrated; the semiconductorheat-dissipating substrate characterized in that pore diameter of theporous tungsten body at a specific cumulative surface area of 95% is 0.3μm or more, and pore diameter of the porous tungsten body at a specificcumulative surface area of 5% is 30 μm or less. Preferably, the porediameter of the porous tungsten body at a specific cumulative surfacearea of 95% is 0.5 μm or more.

[0026] In the above-noted first semiconductor heat-dissipating substrateof the present invention, the content of iron-family metal within thecopper-tungsten alloy may be made 0.02 weight % or less, more preferably0.002 weight % or less. As a result, when the tungsten in thesemiconductor heat-dissipating substrate of the present invention ispresent at 91 to 75 weight %, near the logical value, 210 W/m·K or morein thermal conductivity can be obtained; and when the tungsten ispresent at 81 to 75 weight %, and 230 W/m·K or more thermal conductivitycan be.

[0027] In addition, the present invention provides a methodmanufacturing a semiconductor heat-dissipating substrate made of acopper-tungsten alloy being a porous tungsten body into the pores ofwhich copper has been infiltrated, that is a method of manufacturing asemiconductor heat-dissipating substrate including: a step of mixingtungsten powder and an organic binder; a step of pressure-molding thepowder mixture; a step of heating the molded object to eliminate theorganic binder therefrom; and a step of infiltrating molten copper intothe porous tungsten body being in that state or having beenintermediately sintered; and characterized in that powder of 0.5 μm orless grain size contained in the tungsten powder is present in a 5% orless amount, and powder of 50 μm or more grain size is present in a 5%or less amount.

[0028] In the method of manufacturing the above-noted firstsemiconductor heat-dissipating substrate, iron-family-metal powder maybe further added at less than 0.02 weight % to the tungsten powder, theadditive amount of the iron-family-metal powder preferably being 0.002weight % or less. Further, the amount of the organic binder added to thetungsten powder is preferably 0.2 weight % or less.

[0029] In addition, a second semiconductor heat-dissipating substratethat the present invention provides is characterized in: being made of acopper-tungsten alloy that is a porous tungsten body into the pores ofwhich copper has been infiltrated and composed of asemiconductor-element-carrying central portion and a portion peripheralthereto that differ in substance, the central portion made of copper orof a substance containing more copper than the peripheral portion; andbeing formed integrally without the central portion and the peripheralportion being interrupted by bonding matter.

[0030] In the above-noted second semiconductor heat-dissipatingsubstrate, the substance that composes the central portion and thesubstance that composes the peripheral portion differ in thermalconductivity and/or thermal expansion coefficient. Also, 250 W/m·K ormore in thermal conductivity of the substance that composes the centralportion can be produced with the second semiconductor heat-dissipatingsubstrate.

[0031] In the foregoing second semiconductor heat-dissipating substrate,preferably copper is contained at 30 weight % or more in the centralportion, and copper is contained at less than 30 weight % in theperipheral portion. Further preferable is that copper is contained at 10weight % or less in the peripheral portion. Moreover, preferably thesubstrate is utilized without its peripheral side face undergoinggrinding or polishing procedures, and its dimensional accuracy is ±2 μmper millimeter.

[0032] As a first method among methods that the present inventionprovides of manufacturing the second semiconductor heat-dissipatingsubstrate is a method of manufacturing a semiconductor heat-dissipatingsubstrate composed of a semiconductor-element-carrying central portionand a portion peripheral thereto that differ in substance, characterizedin: forming a porous tungsten body in which vesicle proportion in itscentral portion is made larger than in its peripheral portion by varyingcompression on the central portion and peripheral portion in a processof molding them from a tungsten powder; and infiltrating molten copperinto the porous tungsten body.

[0033] As a second method among methods of manufacturing the foregoingsecond semiconductor heat-dissipating substrate is a method ofmanufacturing a semiconductor heat-dissipating substrate composed of asemiconductor-element-carrying central portion and a portion peripheralthereto that differ in substance, characterized in: forming a poroustungsten body whose central portion and peripheral portion differ incomposition, by varying the percentages of tungsten powder and additivemetal powder in the central portion and the peripheral portion in aprocess of molding them from a tungsten powder; and infiltrating moltencopper into the porous tungsten body obtained.

[0034] As a third method among methods of manufacturing theabove-mentioned second semiconductor heat-dissipating substrate is amethod of manufacturing a semiconductor heat-dissipating substratecomposed of a semiconductor-element-carrying central portion and aportion peripheral thereto that differ in substance, characterized in:infiltrating molten copper into a porous tungsten body obtained in aprocess of molding a tungsten powder by in its central portion forming arecess or otherwise forming a plurality of penetrating ornon-penetrating small holes; and simultaneously filling the recess orsmall holes with copper.

[0035] As a forth method among methods of manufacturing the foregoingsecond semiconductor heat-dissipating substrate is a method ofmanufacturing a semiconductor heat-dissipating substrate composed of asemiconductor-element-carrying central portion and a portion peripheralthereto that differ in substance, characterized in: forming a poroustungsten body centrally having a through-hole; infiltrating moltencopper into the porous tungsten body and afterwards pressing a copperpiece into the central through-hole, or pressing a copper piece into thecentral through-hole in the porous tungsten body and afterwardsinfiltrating it with molten copper; and thereafter heat-treating theporous tungsten body.

[0036] The present invention provides a package utilizing either theforegoing first or second semiconductor heat-dissipating substrate asset forth by the invention, or utilizing a semiconductorheat-dissipating substrate that satisfies the conditions of the first orsecond semiconductor heat-dissipating substrates, wherein a seal ringand an electrode terminal are brazed on the peripheral portion thereof.A package of the present invention is characterized in that warpage insaid semiconductor heat-dissipating substrate after said seal ring andsaid electrode terminal have been brazed onto it is 1 μm or less permillimeter length.

[0037] The present invention, furthermore, provides a submountcharacterized in being furnished with: a submount substrate utilizingeither the foregoing first or second semiconductor heat-dissipatingsubstrate; and a solder layer on anoptical-semiconductor-element-carrying principal face of said submountsubstrate.

[0038] In a submount of the present invention, a chamfer edgewise onsaid optical-semiconductor-element-carrying principal face preferablymeasures 30 μm or less. Further, it is preferable that on at least oneside face of said submount a solder layer is formed continuously fromsaid solder layer on the principal face, or that on all side faces ofsaid submount a solder layer is formed continuously from said solderlayer on the principal face.

[0039] Additionally, the present invention provides a semiconductordevice wherein an optical semiconductor element is mounted in place onthe foregoing submount, and a stem is connected to the reverse face onits opposite side.

BRIEF DESCRIPTION OF DRAWINGS

[0040]FIG. 1 is an explanatory diagram illustrating one specificexample, under the present invention, of a method of manufacturing amolding form utilized in fabricating a semiconductor heat-dissipatingsubstrate composed of a central portion and a peripheral portion thatdiffer in material properties.

[0041]FIG. 2 is an explanatory diagram illustrating another specificexample, under the present invention, of a method of manufacturing amolding form utilized in fabricating a semiconductor heat-dissipatingsubstrate composed of a central portion and a peripheral portion thatdiffer in material properties.

[0042]FIG. 3 is an explanatory diagram illustrating a separate specificexample, under the present invention, of a method of manufacturing amolding form utilized in fabricating a semiconductor heat-dissipatingsubstrate composed of a central portion and a peripheral portion thatdiffer in material properties.

[0043]FIG. 4 is an explanatory diagram illustrating a further separatespecific example, under the present invention, of a method ofmanufacturing a molding form utilized in fabricating a semiconductorheat-dissipating substrate composed of a central portion and aperipheral portion that differ in material properties.

[0044]FIG. 5 is an explanatory diagram illustrating a still furtherspecific example, under the present invention, of a method ofmanufacturing a molding form utilized in fabricating a semiconductorheat-dissipating substrate composed of a central portion and aperipheral portion that differ in material properties.

[0045]FIG. 6 is an explanatory diagram illustrating a yet furtherspecific example, under the present invention, of a method ofmanufacturing a molding form utilized in fabricating a semiconductorheat-dissipating substrate composed of a central portion and aperipheral portion that differ in material properties.

[0046]FIG. 7 is a schematic plan view depicting a chamfered portion of asubmount substrate; wherein (a) illustrates a portion chamfered bygrinding, (b) a portion chamfered by polishing, and (c) a spontaneouslygenerated chamfered portion jagged in form.

[0047]FIG. 8 is a schematic sectional view illustrating an opticalsemiconductor element and a stem being carried on a conventionalsubmount.

[0048]FIG. 9 is a schematic sectional view illustrating an opticalsemiconductor element and a stem being carried on a submount in thepresent invention.

[0049]FIG. 10 depicts a specific example of a package for high-frequencydevices, fabricated utilizing a semiconductor heat-dissipating substratein the present invention; wherein (a) is a schematic plan view thereof,and (b) a schematic side view.

[0050]FIG. 11 depicts another specific example of a package forhigh-frequency devices, fabricated utilizing a semiconductorheat-dissipating substrate in the present invention; wherein (a) is aschematic plan view thereof, and (b) a schematic side view.

[0051]FIG. 12 depicts yet another specific example of a package forhigh-frequency devices, fabricated utilizing a semiconductorheat-dissipating substrate in the present invention; wherein (a) is aschematic plan view thereof, and (b) a schematic side view.

BEST MODE FOR CARRYING OUT THE INVENTION

[0052] As a result of investigating the infiltration of porous tungstenbodies with molten copper during the manufacture of Cu—W alloys, thepresent inventors discovered that the pore diameter of a porous tungstenbody being 0.3 μm or more at a specific cumulative surface area of95%—that is, pores whose diameter is under 0.3 μm being 5% orless—facilitates infiltrating the porous tungsten body with moltencopper, and that compared with the conventional, the occurrence ofinfiltration left unfinished is markedly reduced.

[0053] In addition, because the pore diameter of a porous tungsten bodybeing 0.3 μm or more at a specific cumulative surface area of 95%facilitates copper infiltration, even with an iron-family metal contentof 0.02 weight % or less, copper infiltration can be carried out withoutany problems. This as a result enables drastically reducing the additiveamount of iron-family metal, such as iron, nickel or cobalt—which whilehaving been crucial to improving the wettability of tungsten and copperin order to carry out infiltration with ease, has been the source ofdeterioration in thermal conductivity.

[0054] The pore diameter of a porous tungsten body more preferably being0.5 μm or more at a specific cumulative surface area of 95% totallyeliminates the need to add iron-family metal, and merely withiron-family metal contained as impurity within the tungsten powder, andiron-family metal unavoidably admixed in the course of mixing, even ifthe iron-family metal is 0.002 weight % or less as specific contentcomplete, without any remaining-to-be-infiltrated, copper infiltrationis possible.

[0055] A porous-tungsten-body pore diameter of 30 μm or more at aspecific cumulative surface area of 5%—that is, pores whose diameterexceeds 30 μm being 95% or more—is undesirable because otherwise thecapillary action from the pores decreases, making copper infiltrationimpossible to carry out smoothly, and moreover the strength of theporous tungsten body is weakened, making breakage more liable to occur.

[0056] An average grain size of 5 to 20 μm in the abovementioned poroustungsten bodies is preferable, furthermore; 10 to 20 μm is morepreferable. Having the grain size within this range makes the powderflow better and makes the density during molding uniform, which keepsdeformation during sintering in check. Furthermore, because this allowsthe density of the molded object to be raised even at low moldingpressures, shrinkage due to sintering in order to obtain the density analloy requires will be minimal, consequently curbing deformation duringsintering.

[0057] Because its iron-family metal content may be lessened, a firstsuch semiconductor heat-dissipating substrate made from a Cu—W alloy inthe present invention is endowed with superior thermal conductivitycompared with what is conventional. For example, whereas the thermalconductivity of a conventional W-11 wt. % Cu alloy (approx. 0.2% Nicontent) whose thermal expansion coefficient matches that of alumina hasbeen approximately some 180 W/m·K, with a Cu—W alloy in the presentinvention, a thermal conductivity of 210 W/m·K or more is obtainablewhen the tungsten is 91 to 75 wt. %, and further, 230 W/m·K or more whenthe tungsten is 81 to 75 wt. %.

[0058] The foregoing first semiconductor heat-dissipating substrate madefrom a Cu—W alloy in the present invention may be manufactured usingordinary infiltration methods. Specifically, a porous tungsten body isformed by: mixing tungsten powder and an organic binder, and further,iron-family metal as an additive metal powder according to need;pressure-molding this granulated powder within a mold to form a moldedobject; subsequently heating the molded object to eliminate the organicbinder; and carrying out intermediate sintering further as needed. Acopper-tungsten alloy in substrate form is thereafter obtained byheating and melting an amount of copper sufficient to fill the pores ofthe porous tungsten body, infiltrating the copper into the pores withinthe porous body under agency of the capillary phenomenon and solidifyingit in that state. By thereafter processing this into the required formand shot blasting or barrel polishing it to remove excess copper, asemiconductor heat-dissipating substrate is obtained.

[0059] Rendering the amount of fine powder and coarse powder to be at orbelow a standard is effective for controlling the pore diameter of theporous tungsten body to be within the given specifications noted above.Specifically, rendering the amount of powder 0.5 μm or less in particlediameter contained in the tungsten powder employed as a raw material tobe 5% or less, and moreover the amount of powder 50 μm or less inparticle diameter to be 5% or less, makes for producing a poroustungsten body whose pore diameter at a specific cumulative surface areaof 95% is 0.3 μm or more, and moreover whose pore diameter at a specificcumulative surface area of 5% is 30 μm or less. Rendering the amount ofpowder 3 μm or less in particle diameter to be 5% or less is furthermoredesirable in order that the porous-tungsten-body pore diameter at aspecific cumulative surface area of 95% be 0.5 μm or more.

[0060] Here, in order to enhance the thermal conductivity, impuritiesapart from the copper and tungsten must be curbed to the extentpossible. It is therefore necessary to select a raw material powder inwhich the amount of impurities is slight to the utmost; in particular,using a high-purity tungsten powder whose impurity content is 0.002weight % or less is desirable. The mixing-in of impurities during mixingand granulation process steps must of course be kept in check to theextent possible. And likewise with the organic binder: being thatcarrying out a heating process sufficient for its removal is a matter ofcourse—inasmuch as carbon-containing impurities also lower thermalconductivity, and prove to be a source of warpage as well—it isdesirable to have the additive amount of organic binder beforehand be0.2 weight % or less with respect to the amount of tungsten powder.

[0061] Should the thermal conductivity of a Cu—W alloy having theforegoing singular makeup be inadequate, compositing with anothermaterial such as copper will prove necessary. In that regard, a secondsemiconductor heat-dissipating substrate that the present inventionprovides is composed of a middle portion for carrying semiconductors anda portion peripheral to that, which are of differing materials—theperipheral portion being made of a Cu—W alloy and the middle portionbeing made of either copper or a material that contains more copper thandoes the peripheral portion—and is formed unitarily, without a brazingsubstance such as a brazing layer intervening between the middle portionand the peripheral portion.

[0062] Among materials for composing the middle portion and materialsfor composing the outer portion of a second semiconductorheat-dissipating substrate having such a composition, materials may beselected in a combination so as to differ respectively in thermalconductivity and/or thermal expansion coefficient. By for examplecomposing the middle portion of either copper or a Cu—W alloy thatcontains ample copper, or otherwise another material, a thermalconductivity of 250 W/m·K or more may be obtained. At the same time, byadjusting the thermal expansion coefficient of the peripheral portionthe thermal expansion coefficient of the second semiconductorheat-dissipating substrate can be made to coincide with that of a sealring made of alumina. At the same time this prevents incidents ofwarpage due to incompatibility in thermal expansion coefficient with thematerial that is brazed, it accordingly makes for building packageswhose heat dissipativity is extremely high.

[0063] In semiconductor devices that can handle the increasinglyheightened-output power devices, especially, it is preferable that thecopper quantity in the semiconductor-carrying middle portion of theforegoing second semiconductor heat-dissipating substrate havingsuperior heat dissipativity be 30 weight % or more. This consequentlyyields a substrate whose thermal conductivity in the middle portion is230 W/m·K or more, more preferably, 250 W/m·K or more. It will beunderstood that the copper quantity in the peripheral portion in thiscase would be less than 30 weight %.

[0064] Semiconductor devices generally have a structure in whichsurrounding mechanical devices made of Fe—Ni alloy and Fe—Ni—Co alloyare brazed on. In many situations alumina is used for the surroundingmechanical devices; and alumina, having a thermal expansion coefficientof 6.5×10⁻⁶/° C., matches a Cu—W alloy in which the Cu is 11 weight %,which makes for curbing post-brazing warpage to the utmost. If the Cuquantity in the middle portion that carries semiconductors is made 30 ormore weight %, because its thermal expansion coefficient will be largerthan that of alumina, significant post-brazing warpage will end upoccurring.

[0065] In this respect, in a second semiconductor heat-dissipatingsubstrate in the present invention, by rendering the peripheral portiononto which the surrounding mechanical devices of alumina are brazed aCu—W alloy in which the amount of Cu—which has a smaller thermalexpansion coefficient than that of alumina—is 10 weight % or less, thethermal expansion coefficient of the semiconductor heat-dissipatingsubstrate will be matched in its entirety with alumina, to make forpreventing warpage. Warpage does occur with Fe—Ni alloy and Fe—Ni—Coalloy although not as pronounced as with alumina, because their thermalexpansion coefficients are small, being 8 to 9×10⁻⁶/° C. Given that,utilizing a Cu—W alloy in which the Cu quantity is 15 weight % or lessas the peripheral portion to which Fe—Ni alloy or Fe—Ni—Co alloy isbrazed makes it possible to curb warpage to the utmost.

[0066] In particular, by coordinating the compatibilities, warpage inthe semiconductor heat-dissipating substrate can be curbed to 1 μm orless per millimeter even in the longitudinal direction. Because warpagein the protruding direction lifting the surrounding mechanical devicesis caused by the thermal expansion coefficient of the heat-dissipatingsubstrate being large, reducing the amount of Cu in the peripheralportion of the heat-dissipating substrate to make theheat-dissipating-substrate thermal expansion coefficient smaller makesfor lessening the warpage. Utilizing the foregoing technique alsoenables controlling the warpage direction to be in the direction inwhich the central portion is earthed, which is very efficacious inenhancing heat dissipativity.

[0067] It should be understood that a semiconductor heat-dissipatingsubstrate from a Cu—W alloy must be Ni-plated before brazing.Afterwards, in order to fortify the adhesive strength, it is desirableto carry out a heat treatment, at 750° C. or more, in which the Nidiffuses into the Cu that is a constituent of the Cu—W alloy. Warpagefollowing the heat-treatment at a 750° C. or greater temperature mustnonetheless be held in down to 1 μm or less per millimeter. Becausewarpage when heating arises due, apart from irregularities in density,to residual stress during sintering, it is desirable to slow thepost-infiltration cooling speed and to preheat the alloy at atemperature of 750° C. or more before processing, to eliminate thestress.

[0068] In addition, the second semiconductor heat-dissipating substratemay be utilized without the peripheral side-face going through machiningor polishing process steps, and the dimensional accuracy may be setwithin ±2 μm per millimeter, more preferably within ±1 μm permillimeter.

[0069] A method of manufacturing a second semiconductor heat-dissipatingsubstrate that the present invention provides integrates two kinds ofCu—W alloys, or copper and a Cu—W alloy, in the process of manufacturinga Cu—W alloy based on the way of infiltrating described earlier, andenables manufacturing at low cost semiconductor heat-dissipatingsubstrates whose thermal conductivity is high, and that excel in heatdissipativity.

[0070] Among methods of manufacturing such a second semiconductorheat-dissipating substrate, a first method as for example indicatedschematically in FIGS. 1 and 3 or 4 produces a density differencebetween the middle portion and the peripheral portion, i.e., a moldedobject in which the quantities of vesicles differ, by charging theinterior of a mold with raw-material tungsten powder and whenpressure-molding employing a multi-shaft press imparting a pressuredifference between the middle portion and the peripheral portion.Subsequently infiltrating this porous body with copper makes foryielding a semiconductor heat-dissipating substrate in which two kindsof Cu—W alloys are combined, without undergoing a brazing or likebonding process.

[0071] Likewise, by a second method as for example indicated in FIG. 2,a molded object in which the compositions of the middle portion and theperipheral portion differ is manufactured by utilizing a multi-shaftpress to alter the raw-material powder in the middle portion andperipheral portion—specifically, to alter the proportions of tungstenpowder and additive metal powder—and subsequently the porous body isinfiltrated with copper. With the foregoing first method in which thevesicle quantities are altered by means of a pressure difference duringpressure-molding, too great a pressure difference becomes a source ofcracking; but with the second method in which the compositions of theraw-material powders are altered, a semiconductor heat-dissipatingsubstrate in which Cu—W alloys of two kinds that differ in compositionmay be obtained without altering the quantities of vesicles.

[0072] In furthermore a third method, as for example illustrated in FIG.5, a recess and numerous perforating or non-perforating small holes areformed in pressure-molding tungsten powder, and copper is charged intothe recess and numerous small holes at the same time copper isinfiltrated into the porous body. Further, in a fourth method, as forexample illustrated in FIG. 6, a porous tungsten body is produced, inthe middle portion of which a through-hole is formed either whenpressure-molding the tungsten powder or by thereafter punching or thelike, and after pressure-introducing copper chips into the through-holeand copper-infiltrating the porous body, the entirety is heat-treated.Semiconductor heat-dissipating substrates in which a Cu—W alloy andcopper are combined can be obtained through these methods.

[0073] Nevertheless, to realize the small warpage that the presentinvention makes a feature, the section in which Cu in the middle portionis amply contained and the dimensions of the peripheral portion must bedone according to design. It is therefore desirable to establish theposition of the middle portion in the mold, and then to utilize theperipheral portion without putting it through processing stages such asmachining or polishing. In order to do so, deformation duringintermediate sintering and copper infiltration must be suppressed. Inorder that sintering proceed uniformly, holding iron-group impurities,which become a cause of deformation, down to 0.02 weight % or less isdesirable. This is desirable due to the fact that inasmuch as iron-groupimpurities also turn out to be a source of thermal conductivitydegradation, by adjusting the amount to be 0.02 weight % or less,reduction in thermal conductivity can be curbed.

[0074] Also desirable is to have the mean particle diameter of thetungsten be 5 to 20 μm. Rendering this range of particles uniformizesthe density during molding because the powder flow becomes better andmakes it possible to hold deformation during sintering in check.Moreover, the fact that the density in molding can be raised comparedwith a case in which the mean particle diameter is 5 μm or lessminimizes shrinkage that is due to sintering in order to obtain therequired density, and consequently enables restraint of deformationduring sintering. By keeping the dimensional accuracy of the peripheralportion to ±2 μm or less per millimeter, the semiconductorheat-dissipating substrate can be utilized as it is, without processingthe peripheral side-face.

[0075] Thus, with the first and second semiconductor heat-dissipatingsubstrates according to the present invention, by rendering thesemiconductor-carrying middle portion to have a high thermalconductivity, heat issuing from the semiconductors may be effectivelyeliminated. At the same time, furthermore, rendering the peripheralportion to have a low thermal expansion coefficient makes it possible tohold expansion of the higher-thermal-conductivity middle portion incheck.

[0076] In the majority of cases the foregoing first and secondsemiconductor heat-dissipating substrates of the present invention haveseal rings and electrode terminals made of a ceramic such as alumina andberyllia, or of a Fe—Ni alloy or Fe—Ni—Co alloy brazed onto them,wherein they are utilized as packages. Post-brazing warpage in thesepackages can be held down to 1 μm per millimeter length, and owing totheir excellent thermal conductivity they are superior in heatdissipativity as well.

[0077] In a semiconductor device in which semiconductor circuit elementsare carried on such a package, because the substrate middle portiondirectly beneath the semiconductor elements has high thermalconductivity and because warpage in the substrate is small, adherencewith the semiconductor elements is high, and the device excelsexceedingly in heat dissipativity. In particular, the peripheralportion, and the middle portion that carries semiconductor circuitelements, of the semiconductor heat-dissipating substrate are composedof materials that differ, with the amount of Cu in the middle portionbeing 0.30 weight % or more; and preferably the amount of Cu in theperipheral portion directly beneath the surrounding mechanical devicesis 10 weight % or less, and preferably the surrounding mechanicaldevices are made of alumina.

[0078] Furthermore, a submount furnished with a solder layer on theoptical-semiconductor-element-carrying principal face of a submountsubstrate may be produced utilizing the foregoing first and secondsemiconductor heat-dissipating substrates as the submount substrates.Likewise, furnishing a solder layer on the reverse face on the sideopposite the principal face that carries optical semiconductor elementsmakes it so that a stem can be joined on.

[0079] The surface roughness of the submount substrate is preferably 1μm or less in R_(a), more preferably 0.1 μm or less in R_(a). Likewise,the flatness of the submount substrate is preferably 5 μm of less, morepreferably 1 μm or less. If the surface roughness R_(a) surpasses 1 μm,or the flatness surpasses 5 μm, gaps between the submount and elementswill at times arise when connecting in place optical semiconductorelements such as laser diodes, and the element-cooling effectivenesswill deteriorate. Here, the surface roughness R_(a) and the flatness areprescribed by JIS specifications (JISB0601 and JISB0621, respectively).

[0080] In addition, it is preferable that as shown in FIG. 7 thedimension C of a chamfer on the edge portion of the principal face,which carries an optical semiconductor element, of a submount substrate20 for a submount is 30 μm or less, more preferably 10 μm or less, mostpreferably 5 μm. Since in this case the submount substrate 20 adheresall the way to the edge portion of the optical semiconductor element,there is a sufficiently endothermic effect through the element edgeportion also. Here, the chamfer dimension C is prescribed by JIS (JapanIndustrial Standard) B0001 and B0701.

[0081] Specifically, a chamfer 21 a is formed on the edge portion 21 ofthe principal face, as in FIG. 7(a). The dashed line in FIG. 7(a)indicates a situation in which the chamfer dimension C is 30 μm; and inthe present invention, the chamfer portion 21 a preferably does not gobeyond the dashed line. The form of the chamfer on the edge portion 21,furthermore, may be produced artificially through grinding as is chamfer21 a in FIG. 7(a), or by polishing like chamfer 21 b in FIG. 7(b); orelse the edge portion 21 being chipped into a naturally arising jaggedform as is chamfer 21 c depicted in FIG. 7(c) will also suit. It willalso suit that there is essentially no chamfer portion.

[0082] On the surface of the submount substrate, in order to make securethe joint between the submount and the optical semiconductor element aswell as the stem an adhesive layer can be provided directly in contactwith the surface. The adhesive-layer material may be, to name examples,a material whose bonding affinity with the substrate is satisfactory,and if formed by plating, may be Ni, Ni—Cr, Ni—P, Ni—B, Ni—Co or nickelsulfamate. Likewise, if formed by vapor deposition, the adhesive layermay be Ti, V, Cr, Ni, NiCr alloy, Zr, Nb, or Ta, to name examples. Theadhesive layer is preferably 0.01 to 10 μm, more preferably 1 to 10 μmin thickness.

[0083] Furthermore, an ordinary plating method such as electrolessplating, electroplating, or vibratory barrel plating, or an ordinaryvapor deposition method such as vacuum vapor deposition or sputtering,can be utilized as a method of forming the adhesive layer. The adhesivelayer after it has been formed by plating or vapor deposition ispreferably sintering-treated at 500 to 600° C. under a hydrogenatmosphere, in order to enhance the adhesive strength between theadhesive layer and the submount.

[0084] An anti-dispersion layer can be provided on top of the adhesivelayer, with a solder layer on top of the anti-dispersion layer. Examplesthat can be given of the substantive material for the anti-dispersionlayer include Pt, Au, Pd, Ag and Mo; and a plurality of layer such asPt/Au may be laminated. Any sort of layer-deposition method, such asvapor-deposition or plating may be employed as a method of forming theanti-dispersion layer; but it is preferable to use sputtering, inasmuchas when a layer is deposited on the principal and reverse faces, layersare also deposited on the side faces. The anti-dispersion layerthickness is preferably 0.01 to 10 μm, more preferably 0.05 to 1.5 μm.

[0085] A low-melting-point metal solder such as In or Sn, or an AuSn—,AgSn—, AuGe—, PbSn— or InSn-alloy solder, or a solder in which these arecombined can be utilized as the solder-layer material for joining theoptical semiconductor element and the stem to the submount. Likewise,for the form given the solder layer before it is melted a laminate ofmetals of individual kinds comprising the above-mentioned alloy solderscan be utilized. Here, if an AgSn solder is utilized for the solderlayer, the Ag composition percentage is preferably 72 weight % or less.Likewise, for an AuSn solder, 65 to 85 weight % or 5 to 20 weight % Aupercentage in the composition is preferable. Methods that have beenconventionally used—vapor deposition, sputtering, or plating forexample—can be employed as methods for forming the solder layer.

[0086] In instances of joining an optical semiconductor element or thelike to the submount, as shown for example in FIG. 8, a solder layer 25is effected on the principal and reverse faces of a submount substrate22, on which a Ni layer 23 that is an adhesive layer and a Pt layer 24that is an anti-dispersion layer have been superficially provided; andwherein on the principal face an optical semiconductor element 26, andon the reverse face a stem 27, are joined at the same time, when thesolder connection is made, at for example 330° C. or so, the meltedsolder flows out from between the principal face and the opticalsemiconductor element 26, and bulges into a blob; and this bulgingportion 25 a has sometimes interfered with the emission of light by thebottom-emitting optical semiconductor element 26. Sometimes solderlikewise has flowed out from between the reverse face and the stem 27,forming a bulging portion 25 b in a blob.

[0087] In a submount of the present invention a solder layer isfurnished on the principal face that is to carry an opticalsemiconductor element; meanwhile on at least one side face preferably,and more preferably on all the side faces, a solder layer is formedcontinuously from the solder layer on the principal face. A stem joiningsolder layer is also formed along the reverse face of the submount onthe side opposite the principal face. As a thickness of the solder layeron the semiconductor-element-carrying principal face and thestem-joining reverse face, 0.1 to 10 μm is preferable, while on the sidefaces 0.1 to 2 or so am is preferable.

[0088] Owing to the fact that in this case, as in illustrated in FIG. 9,the solder layer 25 is provided on not just the principal and reversefaces, but also on all the side faces, solder having flowed out frombetween the principal face and the optical semiconductor element 26 whenthe optical semiconductor element 26 and the stem 27 are joined can flowpassing downward along the solder layer 25 on the side faces, andtogether with solder having flowed out from between the reverse face andthe stem 27, bulges atop the stem 27 and forms a meniscus 29 on the fourside faces together. This is true not only in cases in which the opticalsemiconductor element 26 and the stem 27 are joined on simultaneously,but also in cases in which they are joined on sequentially one after theother.

[0089] Accordingly, due to the smooth flow of the solder and to theformation of the meniscus 29, bulges of solder that would interfere withthe emission of light from the optical semiconductor element 26 do notform, and moreover excellent joint strength between the submountsubstrate 22, and the optical semiconductor element 26 and the stem 27,is obtained. Providing the solder layer 25 at least on the one submountside face that is line with the light-emitting face of the opticalsemiconductor element 26 makes possible curbing the formation of asolder bulge that would be a hindrance to the emission of light.Further, in order to heighten the joint strength, 0.01 to 0.2 mm or sois preferable, and 0.03 to 0.2 mm or so is more preferable, for theheight (meniscus dimension) h of the meniscus 29 that forms over thestem 27 in between it and the submount side faces.

[0090] In a situation in which the optical semiconductor element and thestem are mounted/joined onto the submount at the same time, formingsolder layers of an identical kind on all six faces of the submount isdesirable. Moreover, after the optical semiconductor element has beenjoined on through the solder layer provided on principal face of thesubmount, the stem can be joined onto the reverse face utilizing apreform of solder whose melting point is lower. Conversely also, afterthe stem has been joined on, the optical semiconductor element may bemounted in place. In addition, it is possible to connect the opticalsemiconductor element and the stem in place utilizing solder preformswhose melting point is on the same order.

[0091] The optical semiconductor element may be, as representativeexamples, a laser diode or a light-emitting diode. The semiconductorsubstance may be, for example, a semiconductor compound from the III-Vfamily, such as GaAs or InP, or may be a GaN-type semiconductor.Likewise, the optical semiconductor element may be either a top-emittingtype or a bottom-emitting type. It will be understood that if abottom-emitting type of semiconductor device (of the class in which thelight-emitting portion is formed along the laser-diode side that opposeswhere the laser diode and the solder layer join) is used as a laserdiode, the heat dissipativity can be more enhanced, since thelight-emitting portion—which is a heat-emitting portion—will be disposedin a position the nearer to the substrate. An insulating layer of SiO orthe like, and an electrode 2 layer of Au or the like, are formed on thesurface of the optical semiconductor element. It is preferable that thethickness of Au as an electrode layer be 0.1 to 10 μm or so, in order tosecure adequate wettability with the solder layer.

[0092] Metals or ceramics, for example, can be utilized as materials forthe stem. Cu, Al, W, Mo, Fe, Ni, and alloys and composite substancescontaining these metals can be utilized as the metal. Fe—Ni and Ni—Fe—Coare examples that may be given of such alloys; and Cu—W or the like isan example that may be given of such composite substances—which may be,furthermore, Cu—W derived from the present invention. Here it ispreferable that a Ni or Au thin film, or a thin film containing thesemetals, be formed superficially on the stem. These films can be formedby vapor deposition or plating. The thermal conductivity of the stem ispreferably 100 W/m·K or more, and more preferably 200 W/m·K or more.

[0093] A semiconductor device of the present invention, being an opticalsemiconductor element carried on a submount, and on the side oppositethereto a stem joined onto the reverse face, has a superior heatdissipativity that can handle the increasingly heightened-output powerdevices.

[0094] Embodiment 1

[0095] The 8 types of tungsten powder containing the particle diameterdistributions and iron-family impurities set forth in Table I werereadied. Particle diameter distribution in the powders here was measuredusing a laser interferometer system for gaugingparticle-diameter-distribution. The tungsten powder was introduced intoa stirring mixer, and an acrylic organic binder was added at 0.1 weight% with respect to the tungsten powder, which was then mixed 1 hour usingalcohol as a mixing medium, whereby secondary particles approximately 85μm in particle diameter were granulated. The amount of iron-family metalin the impurities contained in each of the obtained granulated powderswas ascertained; admixing in the course of the mixing procedure wasnonexistent, however, with there being no change from when the mixingwas first begun. TABLE I W Particle diameter powder distribution (μm)Iron-family impurities (wt %) no. 5% 50% 95% Fe Ni Co 1 0.22 1.1 1.70.0008 0.0003 0.0001 2 0.92 3.3 8.3 0.0006 0.0001 0.0002 3 1.2 5.8 9.10.0007 0.0003 0.0002 4 2.4 8.3 11.7 0.0007 0.0003 0.0001 5 3.4 11.6 16.40.0009 0.0002 0.0002 6 6.4 22.3 31.5 0.0007 0.0003 0.0002 7 8.8 30.543.0 0.0006 0.0001 0.0001 8 11.2 38.8 54.8 0.0008 0.0001 0.0002

[0096] Subsequently, the above-noted granulated powders were fabricatedinto flat plates 30×15×2 mm by pressure-molding them in a powder-moldingpress. The organic binder was eliminated from these molded objects byheating them in a hydrogen gas stream 1 hour at 400° C., followed by 1hour at 900° C. Intermediate sintering was thereafter carried out in ahydrogen gas stream at 1300° C., yielding respective porous tungstenbodies. The pore-diameter distribution of the obtained porous tungstenbodies was measured employing a mercury porosimeter. It is to be notedthat chipping in the edge portion of the porous tungsten body for whichpowder No. 8 in Table I was utilized, which contained at least 5% poresof 30 μm or more diameter, did occur during handing.

[0097] Next, copper sheet sufficient to fill the volume of vesicles inthe porous tungsten bodies was prepared, the porous tungsten bodies wereset onto the copper sheet and, melting the copper by heating at 1200° C.in a hydrogen gas stream, copper infiltration was carried out to produceCu—W alloys. The incidence of copper infiltration left unfinished inthis case was found and is indicated in Table II below together with thepore-diameter distribution of the porous tungsten bodies, which had beenmeasured earlier. TABLE II W porous body pore-diameter W powderdistribution (μm) Incidence of unfinished no. 5% 50% 95% infiltration(%)  1* 0.99 0.54 0.29 82 2 1.2 0.63 0.33 12 3 1.8 0.82 0.39 8 4 2.00.98 0.43 6 5 2.8 1.2 0.55 0 6 9.1 2.8 0.85 0 7 28.4 6.5 1.45 0  8* 90.415.2 2.51 0

[0098] As is evident from Table II, there were no incidents ofunfinished infiltration in any of the samples, under the presentinvention, of porous tungsten bodies whose pore diameter at a specificcumulative surface area of 95% was 0.5 μm or more, and Whose porediameter at 5% was 30 μm or less (W Powder Nos. 5 through 7); and theincidence of unfinished infiltration in the samples whose pore diameterat a specific cumulative surface area of 95% was 0.3 μm (W Powder Nos. 2through 4) was drastically decreased.

[0099] From these results it is evident that rendering the pore diameterat a specific cumulative surface area of 95% to be 0.3 μm or more, andthe pore diameter at 5% to be 30 μm or less, enhances productivity byreducing the occurrence of unfinished infiltration, and at the same timeachieves sufficient copper infiltration by eliminating occurrences ofunfinished infiltration, even without employing the iron-family metaladded conventionally in order to enhance wettability.

[0100] Embodiment 2

[0101] Iron powder and nickel powder of 1 μm average particle diameter,as iron-family metals, and as necessary, copper powder of 5 μm averageparticle diameter, were added to tungsten powders being W Powder Nos. 2through 7 set forth in the foregoing Table I, in the compositionalproportions indicated in the following Table III. Likewise as withEmbodiment 1, a stirring mixer was employed to add these powders with anacrylic organic binder; and then by mixing 1 hour using alcohol as amixing medium, secondary particles approximately 85 μm in particlediameter were granulated. The amount of iron-family metal in theimpurities contained in each of the obtained granulated powders wasascertained; admixing in the course of the mixing procedure wasnonexistent, however, with there being no change from when the mixingwas first begun.

[0102] These granulated powders were fabricated into flat plates 30×15×2mm by molding them in a powder-molding press. The organic binder waseliminated from these molded objects by heating them in a hydrogen gasstream 1 hour at 400° C., followed by 1 hour at 900° C. Thereafter, aportion of the molded objects were then rendered as is, and a portionwere rendered by intermediately sintering them in a hydrogen gas streamat the temperatures set forth in Table III below, into respective poroustungsten bodies. TABLE III W powder Additive metal (wt. %) IntermediateSample no. Fe Ni Cu sintering temp. (° C.) 1 2 0 0 0 1300 2 3 0 0 0 13003 4 0 0 0 1300 4 5 0 0 0 1300 5 6 0 0 0 1300 6 7 0 0 0 1300 7 5 0 0 01350 8 5 0 0 0 1250 9 5 0 0 0 1200 10 5 0 0 0 1150 11 5 0 0.005 0 130012 5 0 0.01 0 1300 13 5 0 0.015 0 1300 14 5 0 0.02 0 1250 15 6 0 0.02 01250 16 7 0 0.02 0 1250 17 2 0 0.02 0 1250 18 3 0 0.02 0 1250 19 4 00.02 0 1250 20 5 0 0.1 0 1200 21 6 0 0.1 0 1200 22 7 0 0.1 0 1200 23 5 00.1 0 1200 24 5 0 0.1 0 1200 25 5 0 0.1 3 1200 26 5 0 0.1 1 1300 27 5 00 0 1300 28 5 0 0.1 0 1300 29 5 0 0 10 1300 30 5 0 0 15 1300 31 5 0 0 251300 32 5 0 0 35 1300 33 5 0 0 0 —

[0103] Next, copper sheet sufficient to fill the volume of vesicles inthe porous tungsten bodies was prepared, the porous tungsten bodies wereset onto the copper sheet and, melting the copper by heating them at1200° C. in a hydrogen gas stream, copper infiltration was carried outto produce Cu—W alloys. The obtained Cu—W alloys were processed toremove excess copper from the surface, and their densities, thermalconductivities, and thermal expansion coefficients were measured; thoseresults together with quantity of copper infiltrated are set forth inTable IV below. TABLE IV Thermal W expansion Thermal powder Density Cuqty. coefficient conductivity Sample no. (g/cm³) (wt. %) (ppm/° C.)(W/mK) 1 2 17.0 11 6.5 212 2 3 17.0 11 6.5 214 3 4 17.0 11 6.5 215 4 517.0 11 6.5 217 5 6 17.0 11 6.5 215 6 7 17.0 11 6.5 211 7 5 17.7 8 5.7208 8 5 16.4 15 7.8 229 9 5 15.6 20 9.3 244 10 5 15.0 25 10.8 259 11 217.0 11 6.5 212 12 3 17.0 11 6.5 208 13 4 17.0 11 6.5 203 14 5 17.0 116.5 195 15 6 17.0 11 6.5 197 16 7 17.0 11 6.5 199 17 2 17.0 11 6.5 20018 3 17.0 11 6.5 198 19 4 17.0 11 6.5 195 20 5 17.0 11 6.5 182 21 6 17.011 6.5 186 22 7 17.0 11 6.5 188 23 5 17.0 11 6.5 190 24 5 17.0 11 6.5188 25 5 17.0 11 6.5 186 26 5 17.0 11 6.5 190 27 5 17.0 11 6.5 188 28 517.0 11 6.5 190 29 5 16.4 15 7.8 229 30 5 15.6 20 9.3 244 31 5 14.1 3010.5 252 32 5 13.2 40 12.1 273 33 5 17.0 11 6.5 216

[0104] As evident from the foregoing Table m and Table IV, the thermalconductivity at a tungsten content of 91 weight % or less can be raisedto 200 W/m·K or more by having the additive amount of iron-family metalbe less than 0.02 weight %; to 210 W/m·K or more by having the additiveamount be less than 0.01 weight %; and still further (to 217 W/m·K withSample 4 for example) by having the elemental additive amount be zeroand the content of iron-family metal be less than 0.002 weight %.Likewise, the thermal conductivity with the tungsten content being 81weight % or less can be rendered 230 W/m·K or more by having theadditive amount of iron-family metal be less than 0.02 weight %.

[0105] Embodiment 3

[0106] Semiconductor heat-dissipating substrates comprising asemiconductor-element-carrying central portion and a portion peripheralthereto that differ in substantive material were fabricated. In thiscase, molded objects were fabricated by the below-presented methods (1)through (6) in pressure-molding procedures.

[0107] (1) As indicated in FIG. 1, an NC multi-shaft press, in whichagainst an upper punch 1 lower punches 2 a and 2 b operate separately incentral and peripheral sections, was employed; and with thecentral-portion lower punch 2 a being pushed up somewhat as in (a) thepress was charged with a W powder 3, being Powder No. 5 in above-notedTable I; then by pressing the W powder 3 in the press as in (b) to varythe compression in the central and peripheral portions, a molded objectA as in (c), whose density—i.e., vesicle quantity—in the central andperipheral portions differs, was produced.

[0108] (2) As indicated in FIG. 2, the NC multi-shaft press, in whichagainst the upper punch 1 the lower punches 2 a and 2 b operateseparately in central and peripheral sections, was likewise employed;and (a) at first with the central-portion lower punch 2 a being raised,the peripheral portion was charged with a powder 4 mixed according toSample 26 in foregoing Table III; next as in (b), the central-portionlower punch 2 a was lowered, and the cavity formed in the centralportion was charged with a powder 5 mixed according to Sample 27 inforegoing Table III; and by thereafter pressing in the press as in (c),a molded object B as in (d), whose powder composition in the central andperipheral portions differs, was produced.

[0109] (3) As indicated in FIG. 3, an NC multi-shaft press having, foran upper punch 6 a recessed lower punch 7, was employed; and as in (a)the press was charged with a W powder 3, being Powder No. 5 inabove-noted Table I; then by pressing the W powder 3 in the press,varying the compression continuously in the central and peripheralportions as in (b), a molded object C as in (c), whose density—i.e.,vesicle quantity—in the central and peripheral portions differs, wasproduced.

[0110] (4) As indicated in FIG. 4, an NC multi-shaft press, in whichoperate a bulged upper punch 8 and, separately in central and peripheralsections, lower punches 9 a and 9 b, was employed; and with thecentral-portion lower punch 9 a being pushed up somewhat as in (a) thepress was charged with a W powder 3, being Powder No. 5 in above-notedTable I; then by pressing the W powder 3 in the press as in (b) to varythe compression in the central and peripheral portions, a molded objectD as in (c), whose middle has a recess and whose density—i.e., vesiclequantity—in the central and peripheral portions differs, was produced.

[0111] (5) As indicated in FIG. 5, an NC press, furnished with aplurality of perforations in an upper punch 10 and a lower punch 11, andin which core pins 12 of the same diameter as the perforations arestood, was employed; and as in (a) the press was charged with a W powder3, being Powder No. 5 in above-noted Table I; then by press-working asin (b), a molded object E as in (c), having in its central portion aplurality of perforations corresponding to the locations of the corepins 12, was fabricated.

[0112] (6) As indicated in FIG. 6, an NC press, having a hole in thecenter of an upper punch 13 and of a lower punch 14, and in which a corepin 15 of the same diameter as the hole is stood, was employed; and asin (a) the press was charged with a W powder 3, being Powder No. 5 inabove-noted Table I; then by press-working as in (b), a molded objectFas in (c), having in its central portion a through-hole correspondingto the location of the core pin 15, was fabricated.

[0113] From the molded objects thus fabricated the organic binder waseliminated in the same manner as with Embodiment 2, and afterwardscopper was infiltrated into molded objects A through C according to thesame method as with Embodiment 1, and copper was infiltrated into moldedobjects D and E according to the same method as with Embodiment 1 whileat the same time the recesses and perforations were filled with copper.Copper was furthermore infiltrated into molded object F according to thesame method as with Embodiment 1, after which a copper piece of the sameform as the through-hole in the middle was pressed into it and bonded bya heating process carried out at 1050° C.

[0114] Thereafter, shot-blasting employed to remove excess copper stuckon the periphery, and polishing carried out on both the upper and lowersurfaces produced semiconductor heat-dissipating substrates comprising acentral portion and a peripheral portion that differ in substantivematerial, and in between the central and peripheral portions of whichneither a brazing material nor a bonding-substance layer was present.That the thermal conductivity and the thermal expansion coefficient inthe central and peripheral portions of any given one of the obtainedsemiconductor heat-dissipating substrates differed was confirmed.

[0115] Embodiment 4

[0116] Utilizing the W powder (no additive metal) that is Powder No. 5in above-noted Table I, and following method (1) of Embodiment 3, amolded object the central and peripheral portions of which differ invesicle quantity was fabricated; and by infiltrating copper into itlikewise as with Embodiment 1, a semiconductor heat-dissipatingsubstrate was manufactured. The thermal conductivity of thesemiconductor heat-dissipating substrate was 244 W/m·K in the centralportion and 217 W/m·K in the peripheral portion, while the thermalexpansion coefficient was 8.3×10⁻⁶/° C. in the central portion and6.5×10⁻⁶/° C. in the peripheral portion.

[0117] A package and a semiconductor device were actually fabricatedutilizing this semiconductor heat-dissipating substrate. In particular,semiconductor heat-dissipating substrate 30 as represented in FIG. 10,30×15×2 mm was manufactured, and was superficially plated with Ni 1 μmin thickness. A ceramic seal ring 31 made of alumina, and an electrodeterminal 32 made of Fe—Ni—Co alloy were brazed onto the obverse surface,whereby a package for a high-frequency device was fabricated. Theplurality of packages that were produced was assayed for bottom-surfacewarpage, wherein it was confirmed to be 1 μm or less per millimeterlength in any given one. Here, warpage was assayed by placing a testpiece onto a platen and running a dial gauge (scanning distance 29 mm)in the directions of the two diagonals in the rectangular (30 mm×10 mm)principal face, measuring the maximum and minimum values of the heightfrom the platen, finding two values that are the maximum value of theheight-value differences, divided by the gauged length of the diagonals,and taking the larger of values as the sample warpage.

[0118] The package was thereafter plated with Ni and was further platedwith Au. On the semiconductor-element-carrying portion thereof, a chipmade of GaAs was joined with Au—Ge solder. A heat-cycling test in whichtemperature ascent/descent of −65° C.×10 min and +150° C.×10 min wasrepeated 200 cycles was performed, but no abnormalities could bedetected. Subsequently, the semiconductor device was screwed fast to asubstrate made of copper and the GaAs chip was actually put intooperation, wherein normal functioning was confirmed.

[0119] Embodiment 5

[0120] 3 weight % Cu powder of 5 μm average particle diameter was addedto and mixed with W powder of 13 μm average particle diameter,containing as iron-group impurities 6 ppm Fe, 3 ppm Ni and 2 ppm Co.This powder mixture was introduced into a stirring mixer, was joined byan acrylic organic binder at 0.1 weight % with respect to the netweight, and was then mixed 1 hour using alcohol as a mixing medium,whereby secondary particles approximately 85 μm in average particlediameter were fabricated.

[0121] The amount of Fe and Ni in the impurities contained in theobtained powder mixtures was ascertained; admixing in the course of themixing procedure was nonexistent, however, with there being no changefrom when the mixing was first begun. Subsequently, flat-plate-shapedmolded objects 30×15×2.5 mm were fabricated by molding the powders in apowder-molding press. In this case, an NC multi-shaft press, in whichlower punches operate separately in inner and peripheral sections, wasemployed; and by varying the compression on the powder in the centraland peripheral portions 20 kinds of molded objects, whose density—i.e.,vesicle quantity—in the central and peripheral portions differ, wereproduced.

[0122] The binder component was eliminated from the molded objects byheating them in a hydrogen gas stream 1 hour at 400° C., followed by 1hour at 900° C. Next they were sintered in a hydrogen gas stream at1300° C.; copper sheet sufficient to fill the volume of vesicles in thesintered objects was prepared; the sintered objects were set onto thecopper sheet; and by heating to 1200° C. in a hydrogen gas stream, thecopper was infiltrated into the vesicles, whereby Cu—W alloys wereproduced. They were thereafter 900° C. heat-treated for 1 hour, andexcess copper stuck on their periphery was removed employingshot-blasting, whereupon by polishing the upper and lower surfaces,semiconductor heat-dissipating substrates were produced.

[0123] The obtained semiconductor heat-dissipating substrates are asindicated in Table V below: The amount of Cu in the central portion wasof two classes, 35 weight % and 45 weight %, and the thermalconductivity of the central portions was 262 W/m·K and 280 W/m·Krespectively. Likewise, the amount of Cu in the peripheral portion hadvalues of every 1 weight % from 7 weight % through 16 weight %.

[0124] A semiconductor device was actually fabricated utilizing thissemiconductor heat-dissipating substrate. The semiconductor devicerepresented in FIG. 11 has U-shaped grooves 33 a formed in theright/left of a 30 mm×15 mm×2 mm semiconductor heat-dissipatingsubstrate 33 by a machining process. Ni 5 μm in thickness was platedonto this substrate 33, onto which Ni—P 0.5 μm in thickness was furtherplated, and which was thereafter heat-treated at 800° C. in a hydrogengas stream. Next a ceramic seal ring 34 a, and an electrode terminal 35made of Fe—Ni—Co alloy were brazed onto the substrate 33. It wasthereafter plated with Ni and was further plated with Au, whereby apackage for a high-frequency device was fabricated.

[0125] Meanwhile, the semiconductor device represented in FIG. 12 hasholes 33 b formed in the right/left of a 30 mm×15 mm×2 mm semiconductorheat-dissipating substrate 33 by a machining process. This semiconductordevice is different in that in contrast to the FIG. 11 device, a ceramicinsulating plate 36 is brazed in between a seal ring 34 b made ofFe—Ni—Co alloy, and the electrode terminal 35 made of Fe—Ni—Co alloy.

[0126] Bottom-surface warpage on these packages was assayed likewise aswith Embodiment 4 (scanning distance 29 mm), and the results are setforth in Table V below. For warpage direction herein, with the seal ringas up, the direction in which the central portion would make earthingcontact was taken to be the +direction. Making the Cu quantity in theperipheral portion be 15 weight % or less made it possible to make thewarpage 1 μm or less per millimeter. For the case moreover in which thesurrounding mechanical device in FIG. 11 is of alumina, making the Cuquantity in the peripheral portion be 10 weight % or less made itpossible to make the warpage 1 μm or less per millimeter. What is more,the warpage direction could be rendered in the direction the centralportion makes earthing contact. TABLE V Cu qty. (wt. %) CentralPeripheral Post-plating Warpage (μm) Sample portion portion warpage (μm)31 35 7 6 13 22 32 35 8 6 10 20 33 35 9 6 4 15 34 35 10 6 −5 10 35 35 117 −14 2 36 35 12 7 −30 −7 37 35 13 8 −50 −15 38 35 14 8 −73 −19 39 35 158 −95 −25 40 35 16 8 −110 −28 41 45 7 7 5 28 42 45 8 8 0 25 43 45 9 8 −822 44 45 10 8 −15 15 45 45 11 8 −31 13 46 45 12 8 −45 10 47 45 13 8 −602 48 45 14 9 −80 −6 49 45 15 9 −100 −29 50 45 16 9 −120 −35

[0127] Embodiment 6

[0128] W powders of the 6 kinds differing in iron-group impurity andparticle diameter distribution, set forth in Table I from Embodiment 1,were readied. The additive metals set forth in Table VI below were mixedinto these W powders. These powder mixtures were introduced into astirring mixer, was joined by an acrylic organic binder at 0.1 weight %with respect to the net weight, and was then mixed 1 hour using alcoholas a mixing medium, whereby secondary particles approximately 85 μm inaverage particle diameter were fabricated.

[0129] The amount of Fe and Ni in the iron-group impurities contained inthe obtained powder mixtures was ascertained; admixing in the course ofthe mixing procedure was nonexistent, however, with there being nochange from when the mixing was first begun. Subsequently,flat-plate-shaped molded objects 30×15×2.5 mm were fabricated by moldingthese mixed powders in a powder-molding press. In this case, an NCmulti-shaft press, in which lower punches operate separately in innerand peripheral sections, was employed; and by varying the compression onthe powder in the central and peripheral portions, molded objects whosedensity—i.e., vesicle quantity—in the central and peripheral portionsdiffer were produced.

[0130] The binder component was eliminated from the molded objects byheating them in a hydrogen gas stream 1 hour at 400° C., followed by 1hour at 900° C. Next they were sintered in a hydrogen gas stream at1300° C.; copper sheet sufficient to fill the volume of vesicles in thesintered objects was prepared; the sintered objects were set onto thecopper sheet; and by heating to 1200° C. in a hydrogen gas stream, thecopper was infiltrated into the vesicles, whereby Cu—W alloys wereproduced. They were then heat-treated at 900° C. for 1 hour; thereafterby employing shot-blasting to remove excess copper stuck on theirperiphery and polishing the upper and lower surfaces, semiconductorheat-dissipating substrates were produced.

[0131] The amount of Cu in the central portion of the obtainedsemiconductor heat-dissipating substrates was 40 weight %, and thethermal conductivity of the middle part was 273 W/m·K. Likewise, theamount of Cu in the peripheral portion was 8 weight %. The packagerepresented in FIG. 11 for a high-frequency device was fabricatedutilizing the obtained semiconductor heat-dissipating substrates in thesame way as with Embodiment 5.

[0132] The packages were assayed for bottom-surface warpage according tothe same method as with Embodiment 4 (scanning distance 30 mm). Themaximum and minimum values, as well as the average values, from themeasurement results are set forth in the following Table VI. Thedimension in the longitudinal direction was furthermore measured, and avalue that is the difference between the maximum and minimum valuesdivided by the average value was defined to be the dimensionalfluctuation per millimeter. Rendering the amount of iron-group impuritycontained in the semiconductor heat-dissipating substrates be 0.02weight % or less made for dimensional fluctuation of 2 μm or less permillimeter and made for reducing warpage irregularities to 40 μm orless. Moreover, by making the average particle diameter of the W powdersbe 5 to 20 μm warpage fluctuations could be controlled to 20 μm or less;desirably rendering it 10 to 20 μm made bringing dimensionalfluctuations to 1 μm or less per millimeter possible, and enabledcoordinating the direction of warpage. TABLE VI W Additive metalDimensional powder (wt. %) fluctuation Warpage (μm) Sample no. Fe Ni Cu(μm) Max. Min. Avg. 51 2 0 0 3 1.3 25 −10 5 52 3 0 0 3 1.2 18 −8 5 53 40 0 3 0.6 15 0 6 54 5 0 0 3 0.7 14 2 5 55 6 0 0 3 0.8 14 1 6 56 7 0 0 30.9 15 2 6 57 5 0 0.02 0 2.1 28 −15 7 58 5 0 0.02 3 1.9 30 −15 7 59 5 00.1 0 2.5 32 −15 7 60 5 0.1 0 0 2.9 32 −16 7 61 5 0 0.1 3 2.5 32 −17 7

[0133] Embodiment 7

[0134] Submount samples S1 through S25 set forth in the following TableVII in Embodiment 2 were fabricated utilizing the Cu—W materials fromsamples 4, 9, 17 and 20 in Table IV, fabricated in Embodiment 2. Inparticular, the submount substrates were rendered by cutting each Cu—Wmaterial into 1.8×0.6×0.3 mm and chamfering the edge portion at chamferdimension C indicated in FIG. 7.

[0135] The submount substrates were electroplated over their entiresurface with a 2 μm thickness of Ni as an adhesive layer and underwent asintering process under a hydrogen atmosphere at 600° C. Next a thin Ptfilm was formed as an anti-dispersion layer onto the Ni plating bysputtering so as to be a film 1 μm in thickness on the principal andreverse faces, and a film 0.7 μm in thickness on the side faces.

[0136] A solder layer was further formed on the anti-dispersion layer.The substantive material of the solder layer, the film thickness of theprincipal and side surfaces, and the number of formed solder-layer sidefaces, are as entered in Table VII below. Here, a solder layer of thesame thickness as that on the principal face was formed on the reverseface also. Further, the method of forming the solder layer was, forsamples S16, S17 and S18, by sputtering; and for the rest of the samplesentirely, vacuum vapor deposition was employed. TABLE VII Solder layerSide- Cu—W face material Chamfer Principal- No. side film Sam- (Tabledimension face film faces thick- ple V) C(μm) Substance thickness formedness S1 39 <5.0 Au:Sn = 8:2 3.0 4 0.8 S2 34 <5.0 Au:Sn = 8:2 3.0 4 0.8S3 50 <5.0 Au:Sn = 8:2 3.0 4 0.8 S4 47 <5.0 Au:Sn = 8:2 3.0 4 0.8 S5 348 Au:Sn = 8:2 3.0 4 0.8 S6 34 28 Au:Sn = 8:2 3.0 4 0.8 S7 34 40 Au:Sn =8:2 3.0 4 0.8 S8 50 8 Au:Sn = 8:2 3.0 4 0.8 S9 50 28 Au:Sn = 8:2 3.0 40.8 S10 50 40 Au:Sn = 8:2 3.0 4 0.8 S11 47 8 Au:Sn = 8:2 3.0 4 0.8 S1247 28 Au:Sn = 8:2 3.0 4 0.8 S13 47 40 Au:Sn = 8:2 3.0 4 0.8 S14 34 <5.0Au:Sn = 8:2 3.0 4 0.8 S15 34 <5.0 Au:Sn = 8:2 3.0 1 (light- 0.8 emittingface) S16 39 <5.0 Au:Sn = 8:2 4.5 4 2.2 S17 34 <5.0 Au:Sn = 8:2 3.0 41.5 S18 34 <5.0 Au:Sn = 8:2 3.0 4 1.1 S19 34 <5.0 Au:Sn = 8:2 4.0 4 0.5S20 34 <5.0 Au:Sn = 8:2 2.0 4 0.3 S21 34 <5.0 Au:Sn = 8:2 1.0 4 0.8 S2239 <5.0 Ag:Sn = 4:6 3.0 4 0.8 S23 34 <5.0 Ag:Sn = 4:6 3.0 4 0.8 S24 50<5.0 Ag:Sn = 4:6 3.0 4 0.8 S25 47 <5.0 Ag:Sn = 4:6 3.0 4 0.8

[0137] Next, Cu—W base material from the samples fabricated in theembodiments was utilized as a stem for connection to each of thesesubmounts and superficially plated with Au 3 μm in thickness.Furthermore, a GaAs-semiconductor laser diode (LD) element was readied.The LD element is a bottom-emitting type that has an output capacity of400 mW, is width 0.3 mm×length 1.2 mm×thickness 0.15 mm in form, and hasa light-emitting portion in a section 0.03 mm from the bottom face.

[0138] The LD element was joined onto the principal face, and the stemsimultaneously on the reverse face, of each submount by means ofrespective solder layers. The condition of the joint between the stemand the submount, as well as the light-emitting efficiency of the LDelements, in each of the obtained semiconductor devices was evaluated,and the results are set forth in Table VIII below. At first meniscusdimension h was found by measuring the size of the meniscus of solderformed at the joint between the stem and the submount under 100-timesmicroscopic observation.

[0139] The joint strength of the submount with respect to the stem wasmeasured using the Die Shear Test based on MIL-STD-883C method 2019.4,and the average particle diameter of 10 articles of each sample wasfound. A joint strength of 50 MPa or more was denoted by “v. hi”; 40 MPaor more and less than 50 MPa, by “hi”; 30 MPa or more and less than 40MPa, by “med”; and less than 30 MPa, by “low.” Further, thepresence/absence of cracks in the joint portion of the submount stem wassurveyed under 150-times microscopic observation. Crack observations 1in Table VIII are the results of direct post-joining observation; whilecrack observation 2 represents observation results after a heat cyclingtest in which a heat cycle of −40° C.×30 min to +150° C.×30 min wasimplemented 100 rounds.

[0140] Furthermore, 10 semiconductor devices apiece for the remainingsamples were caused to actually emit light, and a count of the elementsthat emitted light and an average value of the light-emitting efficiencywere found. The light-emitting element count indicated, among 20 LDelements mounted together with the samples, a count of those elementsfrom which laser light was emitted with no shielding due to solderbulges on the light-emitting surface. Likewise, luminescence directpost-joining was taken as luminescence 1, while luminescence following aheat-cycle test in which a heat cycle of −40° C.×30 min to +150° C.×30min was implemented 100 rounds was taken as luminescence 2; and any thatwas 80% or more was entered as “v. hi”; 70% or more and less than 80%,as “hi”; 50 or more and less than 70%, as “med”; and less than 50%, as“low.” TABLE VIII Stem-to-submount joint Meniscus Laser diode dimensionJoint Crack Crack Element Conversion Conversion Sample (μm) strengthobservation 1 observation 2 count efficiency 1 efficiency 2 S1 96 v. hiAbsence Absence 20/20 v. hi v. hi S2 104 v. hi Absence Absence 20/20 v.hi v. hi S3 92 v. hi Absence Absence 20/20 hi hi S4 98 v. hi AbsenceAbsence 20/20 hi hi S5 76 v. hi Absence Absence 20/20 v. hi v. hi S6 35v. hi Absence Absence 20/20 hi hi S7 25 hi Absence Absence 20/20 hi medS8 72 v. hi Absence Absence 20/20 hi med S9 36 v. hi Absence Absence20/20 med med S10 22 hi Absence Absence 20/20 med low S11 70 v. hiAbsence Absence 20/20 med med S12 44 v. hi Absence Absence 20/20 med medS13 18 hi Absence Absence 20/20 low low S14 6 low Absence Presence 17/20v. hi v. hi S15 Light- hi Absence Presence 20/20 v. hi v. hi emitting:86; others: 6 S16 192 v. hi Absence Absence 18/20 v. hi v. hi S17 185 v.hi Absence Absence 20/20 v. hi v. hi S18 190 v. hi Absence Absence 20/20v. hi v. hi S19 144 v. hi Absence Absence 20/20 v. hi v. hi S20 72 v. hiAbsence Absence 20/20 v. hi v. hi S21 28 hi Absence Absence 20/20 hi medS22 88 v. hi Absence Absence 20/20 v. hi v. hi S23 100 v. hi AbsenceAbsence 20/20 hi hi S24 92 v. hi Absence Absence 20/20 med med S25 88 v.hi Absence Absence 20/20 med med

INDUSTRIAL APPLICABILITY

[0141] The present invention makes it possible to provide semiconductorheat-dissipating substrates, submounts, and semiconductor devices, madefrom a Cu—W alloy whose thermal conductivity is enhanced over theconventional by eliminating or reducing the addition of iron-familymetal that had been essential to copper infiltration, yet withoutleftover copper and like production problems. Moreover, combining Cu—Walloy and copper in which a plurality of the compositions differ makesfor manufacturing at low cost semiconductor heat-dissipating substratesin which the thermal conductivity and thermal expansion coefficient inthe central portion and in the peripheral portion differ, and makes itpossible to offer packages and semiconductor devices in which warpage issmall and thermal conductivity is high.

1. A semiconductor heat-dissipating substrate made of a copper-tungstenalloy being a porous tungsten body into the pores of which copper hasbeen infiltrated, the semiconductor heat-dissipating substratecharacterized in that pore diameter of said porous tungsten body at aspecific cumulative surface area of 95% is 0.3 μm or more, and porediameter of said porous tungsten body at a specific cumulative surfacearea of 5% is 30 μm or less.
 2. The semiconductor heat-dissipatingsubstrate set forth in claim 1, characterized in that content ofiron-family metal within said copper-tungsten alloy is less than 0.02weight %.
 3. The semiconductor heat-dissipating substrate set forth inclaim 1, characterized in that pore diameter of said porous tungstenbody at a specific cumulative surface area of 95% is 0.5 μm or more. 4.The semiconductor heat-dissipating substrate set forth in claim 3,characterized in that content of iron-family metal within saidcopper-tungsten alloy is 0.002 weight % or less.
 5. The semiconductorheat-dissipating substrate set forth in any of claims 1 through 4,characterized in that the tungsten in said porous tungsten body has anaverage grain size of 5 to 20 μm.
 6. The semiconductor heat-dissipatingsubstrate set forth in any of claims 1 through 5, characterized in thatthe tungsten in said porous tungsten body has an average grain size of10 to 20 μm.
 7. The semiconductor heat-dissipating substrate set forthin any of claims 1 through 6, characterized in that its tungsten ispresent at 91 to 75 weight %, and its thermal conductivity is 210 W/m·Kor more.
 8. The semiconductor heat-dissipating substrate set forth inany of claims 1 through 7, characterized in that its tungsten is presentat 81 to 75 weight %, and its thermal conductivity is 230 W/m·K or more.9. A method of manufacturing a semiconductor heat-dissipating substratemade of a copper-tungsten alloy being a porous tungsten body into thepores of which copper has been infiltrated, the method of manufacturinga semiconductor heat-dissipating substrate including: a step of mixingtungsten powder and an organic binder; a step of pressure-molding thepowder mixture; a step of heating the molded object to eliminate theorganic binder therefrom; and a step of infiltrating molten copper intothe porous tungsten body being in that state or having beenintermediately sintered; and characterized in that powder of 0.5 μm orless particle diameter contained in said tungsten powder is present in a5% or less amount, and powder of 50 μm or more particle diameter ispresent in a 5% or less amount.
 10. The method of manufacturing asemiconductor heat-dissipating substrate set forth in claim 9,characterized in that powder of 3 μm or less particle diameter containedin said tungsten powder is present in a 5% or less amount.
 11. Themethod of manufacturing a semiconductor heat-dissipating substrate setforth in claim 9 or 10, characterized in that iron-family-metal powderis further added at less than 0.02 weight % to said tungsten powder. 12.The method of manufacturing a semiconductor heat-dissipating substrateset forth in claim 11, characterized in that the additive amount of saidiron-family-metal powder is 0.002 weight % or less.
 13. The method ofmanufacturing a semiconductor heat-dissipating substrate set forth inany of claims 9 through 12, characterized in that the amount of saidorganic binder added to said tungsten powder is 0.2 weight % or less.14. A semiconductor heat-dissipating substrate characterized in: beingmade of a copper-tungsten alloy that is a porous tungsten body into thepores of which copper has been infiltrated and composed of asemiconductor-element-carrying central portion and a portion peripheralthereto that differ in substance, said central portion made of copper orof a substance containing more copper than said peripheral portion; andbeing formed integrally without said central portion and said peripheralportion being interrupted by bonding matter.
 15. The semiconductorheat-dissipating substrate set forth in claim 14, characterized in thatthe substance that composes said central portion and the substance thatcomposes said peripheral portion differ in thermal conductivity and/orthermal expansion coefficient.
 16. The semiconductor heat-dissipatingsubstrate set forth in claim 14 or 15, characterized in that thermalconductivity of the substance that composes said central portion is 250W/m·K or more.
 17. The semiconductor heat-dissipating substrate setforth in any of claims 14 through 16, characterized in that copper iscontained at 30 weight % or more in said central portion, and copper iscontained at less than 30 weight % in said peripheral portion.
 18. Thesemiconductor heat-dissipating substrate set forth in any of claims 14through 17, characterized in that copper is contained at 10 weight % orless in said peripheral portion.
 19. The semiconductor heat-dissipatingsubstrate set forth in any of claims 14 through 18, characterized inbeing utilized without its peripheral side face undergoing grinding orpolishing procedures, and in that its dimensional accuracy is ±2 μm permillimeter.
 20. The semiconductor heat-dissipating substrate set forthin claim 19, characterized in that the dimensional accuracy of theperipheral side face is ±1 μm per millimeter.
 21. The semiconductorheat-dissipating substrate set forth in any of claims 14 through 20,characterized in being utilized after being post-nickel-platingheat-treated at a temperature of 750° C. or more, and in that itspost-heat-treatment warpage in its longitudinal direction is 1 μm orless per millimeter.
 22. A method of manufacturing a semiconductorheat-dissipating substrate composed of a semiconductor-element-carryingcentral portion and a portion peripheral thereto that differ insubstance, the method of manufacturing a semiconductor heat-dissipatingsubstrate characterized in: forming a porous tungsten body in whichvesicle proportion in its central portion is made larger than in itsperipheral portion by varying compression on the central portion andperipheral portion in a process of molding them from a tungsten powder;and infiltrating molten copper into said porous tungsten body.
 23. Amethod of manufacturing a semiconductor heat-dissipating substratecomposed of a semiconductor-element-carrying central portion and aportion peripheral thereto that differ in substance, the method ofmanufacturing a semiconductor heat-dissipating substrate characterizedin: forming a porous tungsten body whose central portion and peripheralportion differ in composition, by varying the percentages of tungstenpowder and additive metal powder in the central portion and theperipheral portion in a process of molding them from a tungsten powder;and infiltrating molten copper into the porous tungsten body obtained.24. A method of manufacturing a semiconductor heat-dissipating substratecomposed of a semiconductor-element-carrying central portion and aportion peripheral thereto that differ in substance, the method ofmanufacturing a semiconductor heat-dissipating substrate characterizedin: infiltrating molten copper into a porous tungsten body obtained in aprocess of molding a tungsten powder by in its central portion forming arecess or otherwise forming a plurality of penetrating ornon-penetrating small holes; and simultaneously filling the recess orsmall holes with copper.
 25. A method of manufacturing a semiconductorheat-dissipating substrate composed of a semiconductor-element-carryingcentral portion and a portion peripheral thereto that differ insubstance, the method of manufacturing a semiconductor heat-dissipatingsubstrate characterized in: forming a porous tungsten body centrallyhaving a through-hole; infiltrating molten copper into the poroustungsten body and afterwards pressing a copper piece into the centralthrough-hole, or pressing a copper piece into the central through-holein the porous tungsten body and afterwards infiltrating it with moltencopper; and thereafter heat-treating the porous tungsten body.
 26. Thesemiconductor-heat-dissipating-substrate manufacturing method set forthin any of claims 22 through 25, characterized in heat-treating theporous tungsten body at a temperature of 750° C. or more after—platingit with nickel.
 27. A package utilizing the semiconductorheat-dissipating substrate of claims 1 through 8, or of claims 14through 21, wherein a seal ring and an electrode terminal are brazed onthe peripheral portion of the semiconductor heat-dissipating substrate,or peripherally on the semiconductor-element-carrying central portion.28. A package utilizing a semiconductor heat-dissipating substrate beingthe semiconductor heat-dissipating substrate of claims 14 through 21 andat the same time meeting the terms of claims 1 through 8, wherein a sealring and an electrode terminal are brazed on the peripheral portion ofthe semiconductor heat-dissipating substrate, or peripherally on thesemiconductor-element-carrying central portion.
 29. The package setforth in claim 27 or 28, characterized in that warpage in saidsemiconductor heat-dissipating substrate after said seal ring and saidelectrode terminal have been brazed onto it is 1 μm or less permillimeter length.
 30. The package set forth in any of claims 27 through29, characterized in that said seal ring is made of alumina.
 31. Thepackage set forth in any of claims 27 through 30, characterized in thatits longitudinally-directed warpage is in a direction in which itscentral portion makes earthing contact.
 32. A submount characterized inbeing furnished with: a submount substrate utilizing the semiconductorheat-dissipating substrate of claims 1 through 8, or of claims 14through 21; and a solder layer on anoptical-semiconductor-element-carrying principal face of said submountsubstrate.
 33. The submount set forth in claim 32, characterized in thata chamfer edgewise on said optical-semiconductor-element-carryingprincipal face measures 30 μm or less.
 34. The submount set forth inclaim 32 or 33, characterized in that on at least one side face of saidsubmount a solder layer is formed continuously from said solder layer onthe principal face.
 35. The submount set forth in claim 34,characterized in that on all side faces of said submount a solder layeris formed continuously from said solder layer on the principal face. 36.The submount set forth in any of claims 32 through 35, characterized inthat a solder layer is formed on a reverse face of said submount, on aside thereof opposite said principal face.
 37. The submount set forth inany of claims 32 through 36, characterized in being furnished with anadhesive layer formed in direct superficial contact with said submount.38. The submount set forth in claim 37, characterized in being furnishedwith an anti-dispersion layer between said adhesive layer and saidsolder layer.
 39. A semiconductor device wherein an opticalsemiconductor element is mounted in place on the submount of claims 32through 39, and a stem is connected to the reverse face on its oppositeside.